r8169: use correct barrier between cacheable and non-cacheable memory
r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.
Noticed by Catalin Marinas and Paul Mackerras.
Signed-off-by: David Dillow <firstname.lastname@example.org>
Signed-off-by: David S. Miller <email@example.com>
(cherry picked from commit 4c020a961a812ffae9846b917304cea504c3a733)