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Old 10-29-2009, 05:37 AM
Stephen Hemminger
 
Default sky2: 88E8059 support

Tentative support for newer Marvell hardware including
the Yukon-2 Optima chip. Do not have hatdware to test this yet,
code is based on vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

---
drivers/net/sky2.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++ ++-
1 file changed, 79 insertions(+), 1 deletion(-)

--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -139,6 +139,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_t
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
{ 0 }
};

@@ -602,6 +603,16 @@ static void sky2_phy_init(struct sky2_hw
/* apply workaround for integrated resistors calibration */
gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
+ } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
+ /* apply fixes in PHY AFE */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
+
+ /* apply RDAC termination workaround */
+ gm_phy_write(hw, port, 24, 0x2800);
+ gm_phy_write(hw, port, 23, 0x2001);
+
+ /* set page register back to 0 */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
hw->chip_id < CHIP_ID_YUKON_SUPR) {
/* no effect on Yukon-XL */
@@ -2097,6 +2108,25 @@ out:
spin_unlock(&sky2->phy_lock);
}

+/* Special quick link interrupt (Yukon-2 Optima only) */
+static void sky2_qlink_intr(struct sky2_hw *hw)
+{
+ struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
+ u32 imask;
+ u16 phy;
+
+ /* disable irq */
+ imask = sky2_read32(hw, B0_IMSK);
+ imask &= ~Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, imask);
+
+ /* reset PHY Link Detect */
+ phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
+
+ sky2_link_up(sky2);
+}
+
/* Transmit timeout is only called if we are running, carrier is up
* and tx queue is full (stopped).
*/
@@ -2763,6 +2793,9 @@ static int sky2_poll(struct napi_struct
if (status & Y2_IS_IRQ_PHY2)
sky2_phy_intr(hw, 1);

+ if (status & Y2_IS_PHY_QLNK)
+ sky2_qlink_intr(hw);
+
while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
work_done += sky2_status_intr(hw, work_limit - work_done, idx);

@@ -2812,6 +2845,7 @@ static u32 sky2_mhz(const struct sky2_hw
case CHIP_ID_YUKON_EX:
case CHIP_ID_YUKON_SUPR:
case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
return 125;

case CHIP_ID_YUKON_FE:
@@ -2901,6 +2935,7 @@ static int __devinit sky2_init(struct sk
break;

case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
hw->flags = SKY2_HW_GIGABIT
| SKY2_HW_ADV_POWER_CTL;
break;
@@ -2985,6 +3020,47 @@ static void sky2_reset(struct sky2_hw *h
| GMC_BYP_RETR_ON);
}

+ if (hw->chip_id == CHIP_ID_YUKON_OPT) {
+ u16 reg;
+ u32 msk;
+
+ if (hw->chip_rev == 0) {
+ /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
+
+ /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
+ reg = 10;
+ } else {
+ /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
+ reg = 3;
+ }
+
+ reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
+
+ /* reset PHY Link Detect */
+ sky2_pci_write16(hw, PSM_CONFIG_REG4,
+ reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
+
+
+ /* enable PHY Quick Link */
+ msk = sky2_read32(hw, B0_IMSK);
+ msk |= Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, msk);
+
+ /* check if PSMv2 was running before */
+ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
+#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
+ if (reg & PCI_EXP_LNKCTL_ASPMC) {
+ int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ /* restore the PCIe Link Control register */
+ sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
+ }
+
+ /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
+ }
+
/* Clear I2C IRQ noise */
sky2_write32(hw, B2_I2C_IRQ, 1);

@@ -4403,9 +4479,11 @@ static const char *sky2_name(u8 chipid,
"FE+", /* 0xb8 */
"Supreme", /* 0xb9 */
"UL 2", /* 0xba */
+ "Unknown", /* 0xbb */
+ "Optima", /* 0xbc */
};

- if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
+ if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
else
snprintf(buf, sz, "(chip %#x)", chipid);

--=-=-=
Content-Type: text/plain; name=sky2-add-register-definitions
Content-Disposition: inline; filename=sky2-add-register-definitions
 
Old 10-29-2009, 05:37 AM
Stephen Hemminger
 
Default sky2: 88E8059 support

BugLink: http://bugs.launchpad.net/bugs/537168

Tentative support for newer Marvell hardware including
the Yukon-2 Optima chip. Do not have hatdware to test this yet,
code is based on vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 0f5aac7070a01ec757ed243febe4fff7c944c4d2)

Signed-off-by: Eric Miao <eric.miao@canonical.com>
---
drivers/net/sky2.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ +-
1 files changed, 78 insertions(+), 1 deletions(-)

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 77125b5..1d1bee1 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -139,6 +139,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
{ 0 }
};

@@ -602,6 +603,16 @@ static void sky2_phy_init(struct sky2_hw *hw,
unsigned port)
/* apply workaround for integrated resistors calibration */
gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
+ } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
+ /* apply fixes in PHY AFE */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
+
+ /* apply RDAC termination workaround */
+ gm_phy_write(hw, port, 24, 0x2800);
+ gm_phy_write(hw, port, 23, 0x2001);
+
+ /* set page register back to 0 */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
hw->chip_id < CHIP_ID_YUKON_SUPR) {
/* no effect on Yukon-XL */
@@ -2095,6 +2106,25 @@ out:
spin_unlock(&sky2->phy_lock);
}

+/* Special quick link interrupt (Yukon-2 Optima only) */
+static void sky2_qlink_intr(struct sky2_hw *hw)
+{
+ struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
+ u32 imask;
+ u16 phy;
+
+ /* disable irq */
+ imask = sky2_read32(hw, B0_IMSK);
+ imask &= ~Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, imask);
+
+ /* reset PHY Link Detect */
+ phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
+
+ sky2_link_up(sky2);
+}
+
/* Transmit timeout is only called if we are running, carrier is up
* and tx queue is full (stopped).
*/
@@ -2765,6 +2795,9 @@ static int sky2_poll(struct napi_struct *napi,
int work_limit)
if (status & Y2_IS_IRQ_PHY2)
sky2_phy_intr(hw, 1);

+ if (status & Y2_IS_PHY_QLNK)
+ sky2_qlink_intr(hw);
+
while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
work_done += sky2_status_intr(hw, work_limit - work_done, idx);

@@ -2814,6 +2847,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
case CHIP_ID_YUKON_EX:
case CHIP_ID_YUKON_SUPR:
case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
return 125;

case CHIP_ID_YUKON_FE:
@@ -2903,6 +2937,7 @@ static int __devinit sky2_init(struct sky2_hw *hw)
break;

case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
hw->flags = SKY2_HW_GIGABIT
| SKY2_HW_ADV_POWER_CTL;
break;
@@ -2987,6 +3022,46 @@ static void sky2_reset(struct sky2_hw *hw)
| GMC_BYP_RETR_ON);
}

+ if (hw->chip_id == CHIP_ID_YUKON_OPT) {
+ u16 reg;
+ u32 msk;
+
+ if (hw->chip_rev == 0) {
+ /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
+
+ /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
+ reg = 10;
+ } else {
+ /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
+ reg = 3;
+ }
+
+ reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
+
+ /* reset PHY Link Detect */
+ sky2_pci_write16(hw, PSM_CONFIG_REG4,
+ reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
+
+
+ /* enable PHY Quick Link */
+ msk = sky2_read32(hw, B0_IMSK);
+ msk |= Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, msk);
+
+ /* check if PSMv2 was running before */
+ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
+ if (reg & PCI_EXP_LNKCTL_ASPMC) {
+ int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ /* restore the PCIe Link Control register */
+ sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
+ }
+
+ /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
+ }
+
/* Clear I2C IRQ noise */
sky2_write32(hw, B2_I2C_IRQ, 1);

@@ -4405,9 +4480,11 @@ static const char *sky2_name(u8 chipid, char
*buf, int sz)
"FE+", /* 0xb8 */
"Supreme", /* 0xb9 */
"UL 2", /* 0xba */
+ "Unknown", /* 0xbb */
+ "Optima", /* 0xbc */
};

- if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
+ if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
else
snprintf(buf, sz, "(chip %#x)", chipid);
--
1.7.0

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Old 03-11-2010, 12:17 PM
Sebastian Spaeth
 
Default sky2: 88E8059 support

From: Stephen Hemminger <shemminger@vyatta.com>

Tentative support for newer Marvell hardware including
the Yukon-2 Optima chip. Do not have hatdware to test this yet,
code is based on vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

---
drivers/net/sky2.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++ ++-
1 file changed, 79 insertions(+), 1 deletion(-)

--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -139,6 +139,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_t
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
{ 0 }
};

@@ -602,6 +603,16 @@ static void sky2_phy_init(struct sky2_hw
/* apply workaround for integrated resistors calibration */
gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
+ } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
+ /* apply fixes in PHY AFE */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
+
+ /* apply RDAC termination workaround */
+ gm_phy_write(hw, port, 24, 0x2800);
+ gm_phy_write(hw, port, 23, 0x2001);
+
+ /* set page register back to 0 */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
hw->chip_id < CHIP_ID_YUKON_SUPR) {
/* no effect on Yukon-XL */
@@ -2097,6 +2108,25 @@ out:
spin_unlock(&sky2->phy_lock);
}

+/* Special quick link interrupt (Yukon-2 Optima only) */
+static void sky2_qlink_intr(struct sky2_hw *hw)
+{
+ struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
+ u32 imask;
+ u16 phy;
+
+ /* disable irq */
+ imask = sky2_read32(hw, B0_IMSK);
+ imask &= ~Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, imask);
+
+ /* reset PHY Link Detect */
+ phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
+
+ sky2_link_up(sky2);
+}
+
/* Transmit timeout is only called if we are running, carrier is up
* and tx queue is full (stopped).
*/
@@ -2763,6 +2793,9 @@ static int sky2_poll(struct napi_struct
if (status & Y2_IS_IRQ_PHY2)
sky2_phy_intr(hw, 1);

+ if (status & Y2_IS_PHY_QLNK)
+ sky2_qlink_intr(hw);
+
while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
work_done += sky2_status_intr(hw, work_limit - work_done, idx);

@@ -2812,6 +2845,7 @@ static u32 sky2_mhz(const struct sky2_hw
case CHIP_ID_YUKON_EX:
case CHIP_ID_YUKON_SUPR:
case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
return 125;

case CHIP_ID_YUKON_FE:
@@ -2901,6 +2935,7 @@ static int __devinit sky2_init(struct sk
break;

case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
hw->flags = SKY2_HW_GIGABIT
| SKY2_HW_ADV_POWER_CTL;
break;
@@ -2985,6 +3020,47 @@ static void sky2_reset(struct sky2_hw *h
| GMC_BYP_RETR_ON);
}

+ if (hw->chip_id == CHIP_ID_YUKON_OPT) {
+ u16 reg;
+ u32 msk;
+
+ if (hw->chip_rev == 0) {
+ /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
+
+ /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
+ reg = 10;
+ } else {
+ /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
+ reg = 3;
+ }
+
+ reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
+
+ /* reset PHY Link Detect */
+ sky2_pci_write16(hw, PSM_CONFIG_REG4,
+ reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
+
+
+ /* enable PHY Quick Link */
+ msk = sky2_read32(hw, B0_IMSK);
+ msk |= Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, msk);
+
+ /* check if PSMv2 was running before */
+ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
+#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
+ if (reg & PCI_EXP_LNKCTL_ASPMC) {
+ int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ /* restore the PCIe Link Control register */
+ sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
+ }
+
+ /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
+ }
+
/* Clear I2C IRQ noise */
sky2_write32(hw, B2_I2C_IRQ, 1);

@@ -4403,9 +4479,11 @@ static const char *sky2_name(u8 chipid,
"FE+", /* 0xb8 */
"Supreme", /* 0xb9 */
"UL 2", /* 0xba */
+ "Unknown", /* 0xbb */
+ "Optima", /* 0xbc */
};

- if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
+ if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
else
snprintf(buf, sz, "(chip %#x)", chipid);

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Old 03-11-2010, 04:19 PM
Stephen Hemminger
 
Default sky2: 88E8059 support

On Thu, 11 Mar 2010 14:17:10 +0100
Sebastian Spaeth <Sebastian@SSpaeth.de> wrote:

> + if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)

That was changed to:
if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)


in a later patch

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Old 04-07-2010, 02:05 PM
Eric Miao
 
Default sky2: 88E8059 support

BugLink: http://bugs.launchpad.net/bugs/537168

commit 0f5aac7070a01ec757ed243febe4fff7c944c4d2
Author: Stephen Hemminger <shemminger@vyatta.com>
Date: Thu Oct 29 06:37:09 2009 +0000

sky2: 88E8059 support

Tentative support for newer Marvell hardware including
the Yukon-2 Optima chip. Do not have hatdware to test this yet,
code is based on vendor driver.

Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 3387a2f..53cce74 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -140,6 +140,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
{ 0 }
};

@@ -603,6 +604,16 @@ static void sky2_phy_init(struct sky2_hw *hw,
unsigned port)
/* apply workaround for integrated resistors calibration */
gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
+ } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
+ /* apply fixes in PHY AFE */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
+
+ /* apply RDAC termination workaround */
+ gm_phy_write(hw, port, 24, 0x2800);
+ gm_phy_write(hw, port, 23, 0x2001);
+
+ /* set page register back to 0 */
+ gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
hw->chip_id < CHIP_ID_YUKON_SUPR) {
/* no effect on Yukon-XL */
@@ -2127,6 +2138,25 @@ out:
spin_unlock(&sky2->phy_lock);
}

+/* Special quick link interrupt (Yukon-2 Optima only) */
+static void sky2_qlink_intr(struct sky2_hw *hw)
+{
+ struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
+ u32 imask;
+ u16 phy;
+
+ /* disable irq */
+ imask = sky2_read32(hw, B0_IMSK);
+ imask &= ~Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, imask);
+
+ /* reset PHY Link Detect */
+ phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
+
+ sky2_link_up(sky2);
+}
+
/* Transmit timeout is only called if we are running, carrier is up
* and tx queue is full (stopped).
*/
@@ -2796,6 +2826,9 @@ static int sky2_poll(struct napi_struct *napi,
int work_limit)
if (status & Y2_IS_IRQ_PHY2)
sky2_phy_intr(hw, 1);

+ if (status & Y2_IS_PHY_QLNK)
+ sky2_qlink_intr(hw);
+
while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
work_done += sky2_status_intr(hw, work_limit - work_done, idx);

@@ -2845,6 +2878,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
case CHIP_ID_YUKON_EX:
case CHIP_ID_YUKON_SUPR:
case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
return 125;

case CHIP_ID_YUKON_FE:
@@ -2934,6 +2968,7 @@ static int __devinit sky2_init(struct sky2_hw *hw)
break;

case CHIP_ID_YUKON_UL_2:
+ case CHIP_ID_YUKON_OPT:
hw->flags = SKY2_HW_GIGABIT
| SKY2_HW_ADV_POWER_CTL;
break;
@@ -3024,6 +3059,46 @@ static void sky2_reset(struct sky2_hw *hw)
sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
}

+ if (hw->chip_id == CHIP_ID_YUKON_OPT) {
+ u16 reg;
+ u32 msk;
+
+ if (hw->chip_rev == 0) {
+ /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
+
+ /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
+ reg = 10;
+ } else {
+ /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
+ reg = 3;
+ }
+
+ reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
+
+ /* reset PHY Link Detect */
+ sky2_pci_write16(hw, PSM_CONFIG_REG4,
+ reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
+ sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
+
+
+ /* enable PHY Quick Link */
+ msk = sky2_read32(hw, B0_IMSK);
+ msk |= Y2_IS_PHY_QLNK;
+ sky2_write32(hw, B0_IMSK, msk);
+
+ /* check if PSMv2 was running before */
+ reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
+ if (reg & PCI_EXP_LNKCTL_ASPMC) {
+ int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ /* restore the PCIe Link Control register */
+ sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
+ }
+
+ /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
+ sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
+ }
+
/* Clear I2C IRQ noise */
sky2_write32(hw, B2_I2C_IRQ, 1);

@@ -4442,9 +4517,11 @@ static const char *sky2_name(u8 chipid, char
*buf, int sz)
"FE+", /* 0xb8 */
"Supreme", /* 0xb9 */
"UL 2", /* 0xba */
+ "Unknown", /* 0xbb */
+ "Optima", /* 0xbc */
};

- if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
+ if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
else
snprintf(buf, sz, "(chip %#x)", chipid);

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Old 04-07-2010, 02:15 PM
Chase Douglas
 
Default sky2: 88E8059 support

On Wed, Apr 7, 2010 at 10:05 AM, Eric Miao <eric.miao@canonical.com> wrote:
> BugLink: http://bugs.launchpad.net/bugs/537168
>
> commit 0f5aac7070a01ec757ed243febe4fff7c944c4d2
> Author: Stephen Hemminger <shemminger@vyatta.com>
> Date: * Thu Oct 29 06:37:09 2009 +0000
>
> * *sky2: 88E8059 support
>
> * *Tentative support for newer Marvell hardware including
> * *the Yukon-2 Optima chip. Do not have hatdware to test this yet,
> * *code is based on vendor driver.
>
> * *Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
> * *Signed-off-by: David S. Miller <davem@davemloft.net>
>
> diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
> index 3387a2f..53cce74 100644
> --- a/drivers/net/sky2.c
> +++ b/drivers/net/sky2.c
> @@ -140,6 +140,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
> * * * *{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
> * * * *{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
> * * * *{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
> + * * * { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
> * * * *{ 0 }
> *};
>
> @@ -603,6 +604,16 @@ static void sky2_phy_init(struct sky2_hw *hw,
> unsigned port)
> * * * * * * * */* apply workaround for integrated resistors calibration */
> * * * * * * * *gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
> * * * * * * * *gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
> + * * * } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
> + * * * * * * * /* apply fixes in PHY AFE */
> + * * * * * * * gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
> +
> + * * * * * * * /* apply RDAC termination workaround */
> + * * * * * * * gm_phy_write(hw, port, 24, 0x2800);
> + * * * * * * * gm_phy_write(hw, port, 23, 0x2001);
> +
> + * * * * * * * /* set page register back to 0 */
> + * * * * * * * gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
> * * * *} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
> * * * * * * * * * hw->chip_id < CHIP_ID_YUKON_SUPR) {
> * * * * * * * */* no effect on Yukon-XL */
> @@ -2127,6 +2138,25 @@ out:
> * * * *spin_unlock(&sky2->phy_lock);
> *}
>
> +/* Special quick link interrupt (Yukon-2 Optima only) */
> +static void sky2_qlink_intr(struct sky2_hw *hw)
> +{
> + * * * struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
> + * * * u32 imask;
> + * * * u16 phy;
> +
> + * * * /* disable irq */
> + * * * imask = sky2_read32(hw, B0_IMSK);
> + * * * imask &= ~Y2_IS_PHY_QLNK;
> + * * * sky2_write32(hw, B0_IMSK, imask);
> +
> + * * * /* reset PHY Link Detect */
> + * * * phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
> + * * * sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
> +
> + * * * sky2_link_up(sky2);
> +}
> +
> */* Transmit timeout is only called if we are running, carrier is up
> ** and tx queue is full (stopped).
> **/
> @@ -2796,6 +2826,9 @@ static int sky2_poll(struct napi_struct *napi,
> int work_limit)
> * * * *if (status & Y2_IS_IRQ_PHY2)
> * * * * * * * *sky2_phy_intr(hw, 1);
>
> + * * * if (status & Y2_IS_PHY_QLNK)
> + * * * * * * * sky2_qlink_intr(hw);
> +
> * * * *while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
> * * * * * * * *work_done += sky2_status_intr(hw, work_limit - work_done, idx);
>
> @@ -2845,6 +2878,7 @@ static u32 sky2_mhz(const struct sky2_hw *hw)
> * * * *case CHIP_ID_YUKON_EX:
> * * * *case CHIP_ID_YUKON_SUPR:
> * * * *case CHIP_ID_YUKON_UL_2:
> + * * * case CHIP_ID_YUKON_OPT:
> * * * * * * * *return 125;
>
> * * * *case CHIP_ID_YUKON_FE:
> @@ -2934,6 +2968,7 @@ static int __devinit sky2_init(struct sky2_hw *hw)
> * * * * * * * *break;
>
> * * * *case CHIP_ID_YUKON_UL_2:
> + * * * case CHIP_ID_YUKON_OPT:
> * * * * * * * *hw->flags = SKY2_HW_GIGABIT
> * * * * * * * * * * * *| SKY2_HW_ADV_POWER_CTL;
> * * * * * * * *break;
> @@ -3024,6 +3059,46 @@ static void sky2_reset(struct sky2_hw *hw)
> * * * * * * * *sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
> * * * *}
>
> + * * * if (hw->chip_id == CHIP_ID_YUKON_OPT) {
> + * * * * * * * u16 reg;
> + * * * * * * * u32 msk;
> +
> + * * * * * * * if (hw->chip_rev == 0) {
> + * * * * * * * * * * * /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
> + * * * * * * * * * * * sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
> +
> + * * * * * * * * * * * /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
> + * * * * * * * * * * * reg = 10;
> + * * * * * * * } else {
> + * * * * * * * * * * * /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
> + * * * * * * * * * * * reg = 3;
> + * * * * * * * }
> +
> + * * * * * * * reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
> +
> + * * * * * * * /* reset PHY Link Detect */
> + * * * * * * * sky2_pci_write16(hw, PSM_CONFIG_REG4,
> + * * * * * * * * * * * * * * * *reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
> + * * * * * * * sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
> +
> +
> + * * * * * * * /* enable PHY Quick Link */
> + * * * * * * * msk = sky2_read32(hw, B0_IMSK);
> + * * * * * * * msk |= Y2_IS_PHY_QLNK;
> + * * * * * * * sky2_write32(hw, B0_IMSK, msk);
> +
> + * * * * * * * /* check if PSMv2 was running before */
> + * * * * * * * reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
> + * * * * * * * if (reg & PCI_EXP_LNKCTL_ASPMC) {
> + * * * * * * * * * * * int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
> + * * * * * * * * * * * /* restore the PCIe Link Control register */
> + * * * * * * * * * * * sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
> + * * * * * * * }
> +
> + * * * * * * * /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
> + * * * * * * * sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
> + * * * }
> +
> * * * */* Clear I2C IRQ noise */
> * * * *sky2_write32(hw, B2_I2C_IRQ, 1);
>
> @@ -4442,9 +4517,11 @@ static const char *sky2_name(u8 chipid, char
> *buf, int sz)
> * * * * * * * *"FE+", * * * * */* 0xb8 */
> * * * * * * * *"Supreme", * * */* 0xb9 */
> * * * * * * * *"UL 2", * * * * /* 0xba */
> + * * * * * * * "Unknown", * * */* 0xbb */
> + * * * * * * * "Optima", * * * /* 0xbc */
> * * * *};
>
> - * * * if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
> + * * * if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_OPT)
> * * * * * * * *strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
> * * * *else
> * * * * * * * *snprintf(buf, sz, "(chip %#x)", chipid);
>

Everything here seems to be guarded by the chipid for this new *_OPT
variant, so the regression potential seems slight unless this chip was
actually working for anyone before this patch. However, there's a few
more patches listed at [1] that would be required. Can you send them
on as well?

[1] http://gitorious.org/opensuse/kernel-source/commit/68c33163d0e1e7bf44cf0bb4c6b8497e944d7886

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Old 04-07-2010, 02:29 PM
Eric Miao
 
Default sky2: 88E8059 support

>
> Everything here seems to be guarded by the chipid for this new *_OPT
> variant, so the regression potential seems slight unless this chip was
> actually working for anyone before this patch. However, there's a few
> more patches listed at [1] that would be required. Can you send them
> on as well?
>

The other three patches, I doubt they are relevant to the basic enabling.

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Old 04-07-2010, 02:41 PM
Andy Whitcroft
 
Default sky2: 88E8059 support

On Wed, Apr 07, 2010 at 10:29:40PM +0800, Eric Miao wrote:
> >
> > Everything here seems to be guarded by the chipid for this new *_OPT
> > variant, so the regression potential seems slight unless this chip was
> > actually working for anyone before this patch. However, there's a few
> > more patches listed at [1] that would be required. Can you send them
> > on as well?
> >
>
> The other three patches, I doubt they are relevant to the basic enabling.

Has this patch been tested to work? This makes it sound like not.

-apw

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Old 04-07-2010, 02:46 PM
Eric Miao
 
Default sky2: 88E8059 support

On Wed, Apr 7, 2010 at 10:41 PM, Andy Whitcroft <apw@canonical.com> wrote:
> On Wed, Apr 07, 2010 at 10:29:40PM +0800, Eric Miao wrote:
>> >
>> > Everything here seems to be guarded by the chipid for this new *_OPT
>> > variant, so the regression potential seems slight unless this chip was
>> > actually working for anyone before this patch. However, there's a few
>> > more patches listed at [1] that would be required. Can you send them
>> > on as well?
>> >
>>
>> The other three patches, I doubt they are relevant to the basic enabling.
>
> Has this patch been tested to work? *This makes it sound like not.
>

I'm having a test build, will upload the resulting image soon. But posted
here earlier since you mentioned we need to make this really really quick

> -apw
>

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Old 04-07-2010, 02:56 PM
Chase Douglas
 
Default sky2: 88E8059 support

On Wed, Apr 7, 2010 at 10:46 AM, Eric Miao <eric.miao@canonical.com> wrote:
> On Wed, Apr 7, 2010 at 10:41 PM, Andy Whitcroft <apw@canonical.com> wrote:
>> On Wed, Apr 07, 2010 at 10:29:40PM +0800, Eric Miao wrote:
>>> >
>>> > Everything here seems to be guarded by the chipid for this new *_OPT
>>> > variant, so the regression potential seems slight unless this chip was
>>> > actually working for anyone before this patch. However, there's a few
>>> > more patches listed at [1] that would be required. Can you send them
>>> > on as well?
>>> >
>>>
>>> The other three patches, I doubt they are relevant to the basic enabling.
>>
>> Has this patch been tested to work? *This makes it sound like not.
>>
>
> I'm having a test build, will upload the resulting image soon. But posted
> here earlier since you mentioned we need to make this really really quick

Before we include anything in the Ubuntu kernel, especially as late as
it is, we really need to have at least one person verify that the fix
works as intended. Are you able to test this or have someone else test
it?

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