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-   -   drm/i915: Fix and cleanup DPLL calculation for Ironlake (http://www.linux-archive.org/ubuntu-kernel-team/305485-drm-i915-fix-cleanup-dpll-calculation-ironlake.html)

Stefan Bader 01-06-2010 09:28 PM

drm/i915: Fix and cleanup DPLL calculation for Ironlake
 
From: Zhenyu Wang <zhenyuw@linux.intel.com>

commit 4bfe6b6876a036d26a960320f1ab0bbd752c19bf upstream

When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.

This fixes DPLL clock issue against one monitor at 1680x1050@60hz.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
---
drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++-----------------
1 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ac3b7c..f0ed72f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -804,10 +804,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
intel_clock_t clock;
- int max_n;
- bool found;
int err_most = 47;
- found = false;
+ int err_min = 10000;

/* eDP has only 2 clock choice, no n/m/p setting */
if (HAS_eDP)
@@ -831,16 +829,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
}

memset(best_clock, 0, sizeof(*best_clock));
- max_n = limit->n.max;
- /* based on hardware requriment prefer smaller n to precision */
- for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
- /* based on hardware requirment prefere larger m1,m2, p1 */
- for (clock.m1 = limit->m1.max;
- clock.m1 >= limit->m1.min; clock.m1--) {
- for (clock.m2 = limit->m2.max;
- clock.m2 >= limit->m2.min; clock.m2--) {
- for (clock.p1 = limit->p1.max;
- clock.p1 >= limit->p1.min; clock.p1--) {
+ for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
+ /* based on hardware requriment prefer smaller n to precision */
+ for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
+ /* based on hardware requirment prefere larger m1,m2 */
+ for (clock.m1 = limit->m1.max;
+ clock.m1 >= limit->m1.min; clock.m1--) {
+ for (clock.m2 = limit->m2.max;
+ clock.m2 >= limit->m2.min; clock.m2--) {
int this_err;

intel_clock(dev, refclk, &clock);
@@ -849,18 +845,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
this_err = abs((10000 - (target*10000/clock.dot)));
if (this_err < err_most) {
*best_clock = clock;
- err_most = this_err;
- max_n = clock.n;
- found = true;
/* found on first matching */
goto out;
+ } else if (this_err < err_min) {
+ *best_clock = clock;
+ err_min = this_err;
}
}
}
}
}
out:
- return found;
+ return true;
}

/* DisplayPort has only two frequencies, 162MHz and 270MHz */
--
1.6.3.3


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