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Old 06-03-2008, 11:32 PM
Alok Kataria
 
Default x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs

OriginalAuthor: Andi Kleen <ak@suse.de>
Commit: de4218634e3df6d73a3e6cdfdf3a17fa3bc7e013

According to AMD RDTSC can be synchronized through MFENCE.
Implement the necessary CPUID bit for that.

Signed-off-by: Alok N Kataria <akataria@vmware.com>
---
arch/x86/kernel/cpu/amd.c | 3 +++
arch/x86/kernel/setup_64.c | 4 ++--
include/asm-x86/cpufeature_32.h | 1 +
3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1ff88c7..aaa8101 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -301,6 +301,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* K6s reports MCEs but don't actually have all the MSRs */
if (c->x86 < 6)
clear_bit(X86_FEATURE_MCE, c->x86_capability);
+
+ if (cpu_has_xmm)
+ set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
}

static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index ec976ed..65b587b 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -681,8 +681,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
set_bit(X86_FEATURE_K8, &c->x86_capability);

- /* RDTSC can be speculated around */
- clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ /* MFENCE stops RDTSC speculation */
+ set_bit(X86_FEATURE_MFENCE_RDTSC, &c->x86_capability);

/* Family 10 doesn't support C states in MWAIT so don't use it */
if (c->x86 == 0x10 && !force_mwait)
diff --git a/include/asm-x86/cpufeature_32.h b/include/asm-x86/cpufeature_32.h
index f17e688..08622c8 100644
--- a/include/asm-x86/cpufeature_32.h
+++ b/include/asm-x86/cpufeature_32.h
@@ -82,6 +82,7 @@
/* 14 free */
#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
+#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
--
1.5.4




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