ICE in reload_cse_simplify_operands, at postreload.c:392
 

------- Comment #7 from dave at hiauly1 dot hia dot nrc dot ca 2007-11-24 19:27 -------
Subject: Re: [4.2/4.3 Regression] ICE in
reload_cse_simplify_operands, at postreload.c:392

The attached patch seems to fix the problem on the trunk. However,
it doesn't work on 4.2. It makes the problem reported in PR middle-end/32889
worse and I get bootstrap failure in stage2.

I've experimented with reload patterns to handle (mem (plus reg const))
but this doesn't seem to help with 32889. So, I think there's a problem
with the handling of reg_equiv_alt_mem_list in 4.2.

Dave


------- Comment #8 from dave at hiauly1 dot hia dot nrc dot ca 2007-11-24 19:27 -------
Created an attachment (id=14631)
--> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=14631&action=view)


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ICE in reload_cse_simplify_operands, at postreload.c:392
 

------- Comment #9 from ebotcazou at gcc dot gnu dot org 2007-11-24 20:31 -------
> This probably means I don't have the change quite right. I also have a
> problem with paradoxical SUBREGS when the inner register is spilled. I'm
> not clear on how this is to be handled on a big endian target with strict
> alignment. The documentation says reload is supposed to prevent this from
> happening, but it doesn't seem to. I see this with the testcase from this
> PR. It's combine that creates the paradoxical SUBREG.

Here is how the SPARC port deals with this specific case:

/* Return the register class of a scratch register needed to load IN into
a register of class CLASS in MODE.

We need a temporary when loading/storing a HImode/QImode value
between memory and the FPU registers. This can happen when combine puts
a paradoxical subreg in a float/fix conversion insn.

We need a temporary when loading/storing a DFmode value between
unaligned memory and the upper FPU registers. */

#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN)

[...]

#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN)


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ebotcazou at gcc dot gnu dot org changed:

What |Removed |Added
----------------------------------------------------------------------------
CC| |ebotcazou at gcc dot gnu dot
| |org


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ICE in reload_cse_simplify_operands, at postreload.c:392
 

------- Comment #11 from ebotcazou at gcc dot gnu dot org 2007-11-24 21:47 -------
> Is there a reason why you want to load/store HImode/QImode values in
> the FPU registers on sparc? On the pa, there aren't any insns that
> operate on them. So, the only reason we supported this was because
> these modes are tied to SImode and DImode.

Same on SPARC, there are no HImode/QImode move insns either.

> I haven't seen the paradoxical subreg in a float/fix conversion
> insns with the current patch. I did see this in some of the first
> versions of pa_cannot_change_mode_class. I think I eliminated
> this problem by prevent mode changes in the FP registers:
>
> if (MAYBE_FP_REG_CLASS_P (class))
> return true;
>
> Due you think this problem is latent?

On SPARC or on the PA even with CANNOT_CHANGE_MODE_CLASS?


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ICE in reload_cse_simplify_operands, at postreload.c:392
 

------- Comment #12 from dave at hiauly1 dot hia dot nrc dot ca 2007-11-24 22:14 -------
Subject: Re: [4.2/4.3 Regression] ICE in reload_cse_simplify_operands, at
postreload.c:392

> > I haven't seen the paradoxical subreg in a float/fix conversion
> > insns with the current patch. I did see this in some of the first
> > versions of pa_cannot_change_mode_class. I think I eliminated
> > this problem by prevent mode changes in the FP registers:
> >
> > if (MAYBE_FP_REG_CLASS_P (class))
> > return true;
> >
> > Due you think this problem is latent?
>
> On SPARC or on the PA even with CANNOT_CHANGE_MODE_CLASS?

I meant on the PA using the CANNOT_CHANGE_MODE_CLASS patch.

What I saw when mode changes were allowed was something like
the following:

set (subreg:SI (mem:HI)) (fix:SI (fix:SF))

where the mem was a spilled HImode pseudo. At the time,
I thought I had stopped mode changes to QImode/HImode in
the FPU registers but I believe they got tied to DImode.

Dave


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